As use of consumer and commercial electronic devices, such as computers, smart-phones, tablets, and the like, increases, the demand for greater amount of random access memory (RAM) increases to meet application requirements. However, RAM size and form factor must be scaled down to account for weight considerations in these electronic devices, i.e., the same amount of RAM must be created on a smaller size semiconductor to reduce weight. As the entirety of a RAM module is scaled down, the components of the RAM module must also be scaled down.
Generally a RAM module is composed of a plurality of memory tiles. Each of the memory tiles further comprises an array of memory cells. The memory cells each represent a “bit” in memory and contain electrode contacts. Each memory cell comprises a top electrode and a bottom electrode surface, with active cell materials between the top electrode and the bottom electrode. In scaling down RAM, oftentimes the top and bottom electrodes are reduced in size to increase memory density within a memory die. In fabricating a wafer comprised of a plurality of memory arrays with increasingly smaller electrode contacts, for each memory cell, a small via is etched into an insulating material, for example, a dielectric material. The etched via is then filled with a conductive material to form the bottom electrode using chemical vapor deposition (CVD). During the process, the conductive material film grows radially from the sidewalls of the via outward towards the center, and grows vertically from the bottom of the via. As the CVD nears completion, the chemical film generally leaves a keyhole of variable size at the center of the etched via. The chemical film is polished via chemical-mechanical planarization (CMP) so that the film only remains in the via. The CMP oftentimes creates a chemical interaction with the chemical film that increases voiding and the size of the keyhole opening. Each keyhole opening, however, varies depending on how each contact was formed, how the grains of the chemical films are nucleated and how fast the chemical film grows in each via. The different nucleations of the chemical film differ in each via and introduce variability across a semiconductor wafer, leading to unpredictable electrical characteristics such as a distribution of different cell currents and broader switching voltage range.
Additionally, in resistive ram (ReRAM), it is desired to minimize resistance to improve RC delay, minimize latency and the like. However, the direct contact between the solid plug with the active cell material makes it difficult to decouple the chemical and electronic aspects of the electrode interface from the bulk resistance of the entire plug.
Therefore, there is a need in the art for reducing the variability of electrical characteristics across a semiconductor wafer and decoupling the chemical and electronic aspects of the electrode interface in accordance with exemplary embodiments of the present invention.